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Defined in VHDL/ACIA_TX.vhd
| library ieee | |
| use ieee.numeric_std.all | |
| use ieee.std_logic_1164.all | |
| use ieee.std_logic_unsigned.all |
| Clk | in | Std_Logic |
| TxRst | in | Std_Logic |
| TxWr | in | Std_Logic |
| TxDin | in | Std_Logic_Vector(7 downto 0) |
| WdFmt | in | Std_Logic_Vector(2 downto 0) |
| BdFmt | in | Std_Logic_Vector(1 downto 0) |
| TxClk | in | Std_Logic |
| TxDat | out | Std_Logic |
| TxEmp | out | Std_Logic |