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Entity work.twi

Syntheziable VHDL two wire interface

Defined in VHDL/twi-master.vhd

Author: John E. Kent
Version: 0.2 from 2010-08-09

Architectures

rtl


Libraries and global use clauses

library ieee
use ieee.numeric_std.all
use ieee.std_logic_1164.all
library unisim
use unisim.vcomponents.all

Generics

CLK_FREQ integer := 25_000_000

Ports

clk instd_logic
CPU signals
rst instd_logic
CPU signals
cs instd_logic
CPU signals
rw instd_logic
CPU signals
irq outstd_logic
CPU signals
addr instd_logic
CPU signals
data_in instd_logic_vector(7 downto 0)
CPU signals
data_out outstd_logic_vector(7 downto 0)
CPU signals
scl inoutstd_logic
I2C Signals
sda inoutstd_logic
I2C Signals

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