Entity work.twi
Syntheziable VHDL two wire interface
Defined in VHDL/twi-master.vhd
Author: John E. Kent
Version: 0.2 from 2010-08-09
Architectures
Libraries and global use clauses
library ieee |
use ieee.numeric_std.all |
use ieee.std_logic_1164.all |
library unisim |
use unisim.vcomponents.all |
Generics
CLK_FREQ |
integer |
:= 25_000_000 |
Ports
clk |
in | std_logic |
| CPU signals |
rst |
in | std_logic |
| CPU signals |
cs |
in | std_logic |
| CPU signals |
rw |
in | std_logic |
| CPU signals |
irq |
out | std_logic |
| CPU signals |
addr |
in | std_logic |
| CPU signals |
data_in |
in | std_logic_vector(7 downto 0) |
| CPU signals |
data_out |
out | std_logic_vector(7 downto 0) |
| CPU signals |
scl |
inout | std_logic |
| I2C Signals |
sda |
inout | std_logic |
| I2C Signals |
Generated on 1 Jan 2018 19:48:42 with VHDocL
V0.2.6