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Architecture rtl of work.ACIA_6850

Architecture for ACIA_6850 Interface registers

Defined in VHDL/ACIA_6850.vhd

Authors: Ovidiu Lupas, John Kent
Version: 4.2 from 25 February 2007


Detailed description

Implements an RS232 Asynchronous serial communications device

Instantiated in...

work.my_system09 (rtl)

Libraries and global use clauses

library ieee
use ieee.numeric_std.all
use ieee.std_logic_1164.all

Type declarations

typeDCD_State_Typeis ( DCD_State_Idle, DCD_State_Int, DCD_State_Reset )

Component declarations

ACIA_RX
ACIA Receiver
Default binding: work.ACIA_RX
ACIA_TX
ACIA Transmitter
Default binding: work.ACIA_TX

Processes

ACIA_Reset ( clk, rst, Reset, DCD_n )
ACIA Reset may be hardware or software
ACIA_Status (Reset, clk )
ACIA Status Register ACIA_Status : process(clk, Reset, TxIEnb, RxIEnb, RxDR, TxBE, DCD_n, CTS_n, DCDInt, FErr, OErr, PErr )
ACIA_Control ( CtrlReg, TxDbit )
ACIA Transmit Control
ACIA_Read_Write (clk, Reset )
Generate Read / Write strobes.
ACIA_Read_Write: process(clk, Reset, cs, rw, Addr, DataIn )
ACIA_Data_Mux (Addr, StatReg, RecvReg)
Set Data Output Multiplexer
ACIA_DCD_edge ( reset, clk )
Data Carrier Detect Edge rising edge detect ACIA_DCD_edge : process( reset, clk, DCD_n, DCDDel )
ACIA_DCD_Int ( reset, clk )
Data Carrier Detect Interrupt If Data Carrier is lost, an interrupt is generated To clear the interrupt, first read the status register then read the data receive register ACIA_DCD_Int : process( reset, clk, DCDState, DCDEdge, ReadRR, ReadSR )

Instantiations

RxDev : ACIA_RX
Binding: work.ACIA_RX (rtl)
TxDev : ACIA_TX
Binding: work.ACIA_TX (rtl)

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