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Architecture rtl of work.twi

Implements an I2C master Interface

Defined in VHDL/twi-master.vhd

Author: John E. Kent
Version: 0.2 from 2010-08-09


Libraries and global use clauses

library ieee
use ieee.numeric_std.all
use ieee.std_logic_1164.all
library unisim
use unisim.vcomponents.all

Processes

ACIA_Reset (clk, rst)
ACIA Reset may be hardware or software
ACIA_Status (Reset, clk)
ACIA Status Register
ACIA_Control (CtrlReg, TxDbit)
ACIA Transmit Control
tx_process (clk, reset)
ACIA_Read_Write (clk, Reset)
Generate Read / Write strobes.
ACIA_Data_Mux (Addr, RecvReg, StatReg)
Set Data Output Multiplexer
ACIA_DCD_edge (reset, clk)
Data Carrier Detect Edge rising edge detect
ACIA_DCD_Int (reset, clk)
Data Carrier Detect Interrupt
If Data Carrier is lost, an interrupt is generated. To clear the interrupt, first read the status register then read the data receive register.

Instantiations

RxDev : entity ACIA_RX (rtl)
TxDev : entity ACIA_TX (rtl)

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