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Defined in VHDL/ACIA_RX.vhd
| library ieee | |
| use ieee.numeric_std.all | |
| use ieee.std_logic_1164.all | |
| use ieee.std_logic_unsigned.all |
| Clk | in | Std_Logic |
| RxRst | in | Std_Logic |
| RxRd | in | Std_Logic |
| WdFmt | in | Std_Logic_Vector(2 downto 0) |
| BdFmt | in | Std_Logic_Vector(1 downto 0) |
| RxClk | in | Std_Logic |
| RxDat | in | Std_Logic |
| RxFErr | out | Std_Logic |
| RxOErr | out | Std_Logic |
| RxPErr | out | Std_logic |
| RxRdy | out | Std_Logic |
| RxDout | out | Std_Logic_Vector(7 downto 0) |