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Top level file for quad Core 6809 compatible system on a chip
Defined in VHDL/quadcpu09.vhd
Designed for Xilinx XC3S1000 Spartan 3 FPGA. Intended for Digilent Xilinx Spartan 3 Starter FPGA board, or XESS XSA-3S1000 FPGA board.
library ieee | |
use ieee.numeric_std.all | |
use ieee.std_logic_1164.all | |
use ieee.std_logic_arith.all | |
use ieee.std_logic_unsigned.all | |
library unisim | |
use unisim.vcomponents.all | |
library work | |
use work.bit_funcs.all |
type | addr_type | is | std_logic_vector(ADDR_WIDTH-1 downto 0) |
type | data_type | is | std_logic_vector(DATA_WIDTH-1 downto 0) |
type | cpu_type | is | std_logic_vector( CPU_MAX-1 downto 0) |
type | addr_array | is | array(0 to (CPU_MAX-1)) of addr_type |
type | data_array | is | array(0 to (CPU_MAX-1)) of data_type |
CPU_MAX | integer | := 4 |
ADDR_WIDTH | integer | := 20 |
DATA_WIDTH | integer | := 8 |
my_unicpu09 |
my_pri_rotate ( rst, clk ) | ||||
Rotating priority | ||||
my_pri_mux ( pri_cnt ) | ||||
Rotate VMA request | ||||
my_pri_encoder ( pri_mux ) | ||||
Priority Encode Rotated VMA Request | ||||
my_bus_grant ( rst, clk ) | ||||
Grant highest priority requesting processor access to the bus | ||||
my_hold_machine ( rst, clk ) | ||||
Hold processor until bus cycle acknowledged |
my_unicpu09_0 : unicpu09 | ||||
Binding: work.unicpu09 (RTL) | ||||
my_unicpu09_1 : unicpu09 | ||||
Binding: work.unicpu09 (RTL) | ||||
my_unicpu09_2 : unicpu09 | ||||
Binding: work.unicpu09 (RTL) | ||||
my_unicpu09_3 : unicpu09 | ||||
Binding: work.unicpu09 (RTL) |