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Synthesizable Single 6809 Instruction Compatible CPU Module
Defined in VHDL/unicpu09.vhd
Author: John E. Kent
Version: 0.2 from 2010-06-16
| library ieee | |
| use ieee.numeric_std.all | |
| use ieee.std_logic_1164.all | |
| use ieee.std_logic_arith.all | |
| use ieee.std_logic_unsigned.all | |
| library unisim | |
| use unisim.vcomponents.all |
| clk | in | std_logic | |
| rst | in | std_logic | |
| id | in | std_logic_vector( 7 downto 0) | |
| cpu side signals | |||
| vma | out | std_logic | |
| cpu side signals | |||
| rw | out | std_logic | |
| cpu side signals | |||
| addr | out | std_logic_vector(19 downto 0) | |
| cpu side signals | |||
| mem_vma | in | std_logic | |
| memory side signals | |||
| mem_rw | in | std_logic | |
| memory side signals | |||
| mem_addr | in | std_logic_vector(19 downto 0) | |
| memory side signals | |||
| mem_data_in | in | std_logic_vector(7 downto 0) | |
| memory side signals | |||
| mem_data_out | out | std_logic_vector(7 downto 0) | |
| memory side signals | |||
| halt | in | std_logic | |
| controls | |||
| hold | in | std_logic | |
| controls | |||
| irq | in | std_logic | |
| controls | |||
| nmi | in | std_logic | |
| controls | |||
| firq | in | std_logic | |
| controls | |||