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Synthesizable Quad Core 6809 instruction compatible CPU Module
Defined in VHDL/quadcpu09.vhd
Author: John E. Kent
Version: 0.2 from 30th May 2010
quadcpu09 is a top level entity for a quad CPU09 core written in VHDL.
Still under development
| library ieee | |
| use ieee.numeric_std.all | |
| use ieee.std_logic_1164.all | |
| use ieee.std_logic_arith.all | |
| use ieee.std_logic_unsigned.all | |
| library unisim | |
| use unisim.vcomponents.all | |
| library work | |
| use work.bit_funcs.all |
| clk | in | std_logic |
| rst | in | std_logic |
| vma | out | std_logic |
| addr | out | std_logic_vector(19 downto 0) |
| rw | out | std_logic |
| data_in | in | std_logic_vector(7 downto 0) |
| data_out | out | std_logic_vector(7 downto 0) |
| irq | in | std_logic |
| nmi | in | std_logic |
| firq | in | std_logic |
| halt | in | std_logic |
| hold | in | std_logic |