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Entity work.dualport

Dual-port front-end for SDRAM controller.

Defined in System09_base/sdramcntl.vhd

Author: Dave Vanden Bout
Version: 1.0.0 from 06/01/2005

Detailed description

Supports two independent I/O ports to the SDRAM.

Architectures

arch

Libraries and global use clauses

library IEEE
use IEEE.numeric_std.all
use IEEE.std_logic_1164.all
use IEEE.std_logic_unsigned.all
library UNISIM
use WORK.common.all

Generics

PIPE_EN	boolean	:= false
PORT_TIME_SLOTS	std_logic_vector(15 downto 0)	:= "1111000011110000"
DATA_WIDTH	natural	:= 16
HADDR_WIDTH	natural	:= 23

Ports

clk	in	std_logic
rst0	in	std_logic
	host-side port 0
rd0	in	std_logic
	host-side port 0
wr0	in	std_logic
	host-side port 0
earlyOpBegun0	out	std_logic
	host-side port 0
opBegun0	out	std_logic
	host-side port 0
rdPending0	out	std_logic
	host-side port 0
done0	out	std_logic
	host-side port 0
rdDone0	out	std_logic
	host-side port 0
hAddr0	in	std_logic_vector(HADDR_WIDTH-1 downto 0)
	host-side port 0
hDIn0	in	std_logic_vector(DATA_WIDTH-1 downto 0)
	host-side port 0
hDOut0	out	std_logic_vector(DATA_WIDTH-1 downto 0)
	host-side port 0
status0	out	std_logic_vector(3 downto 0)
	host-side port 0
rst1	in	std_logic
	host-side port 1
rd1	in	std_logic
	host-side port 1
wr1	in	std_logic
	host-side port 1
earlyOpBegun1	out	std_logic
	host-side port 1
opBegun1	out	std_logic
	host-side port 1
rdPending1	out	std_logic
	host-side port 1
done1	out	std_logic
	host-side port 1
rdDone1	out	std_logic
	host-side port 1
hAddr1	in	std_logic_vector(HADDR_WIDTH-1 downto 0)
	host-side port 1
hDIn1	in	std_logic_vector(DATA_WIDTH-1 downto 0)
	host-side port 1
hDOut1	out	std_logic_vector(DATA_WIDTH-1 downto 0)
	host-side port 1
status1	out	std_logic_vector(3 downto 0)
	host-side port 1
rst	out	std_logic
	SDRAM controller port
rd	out	std_logic
	SDRAM controller port
wr	out	std_logic
	SDRAM controller port
earlyOpBegun	in	std_logic
	SDRAM controller port
opBegun	in	std_logic
	SDRAM controller port
rdPending	in	std_logic
	SDRAM controller port
done	in	std_logic
	SDRAM controller port
rdDone	in	std_logic
	SDRAM controller port
hAddr	out	std_logic_vector(HADDR_WIDTH-1 downto 0)
	SDRAM controller port
hDIn	out	std_logic_vector(DATA_WIDTH-1 downto 0)
	SDRAM controller port
hDOut	in	std_logic_vector(DATA_WIDTH-1 downto 0)
	SDRAM controller port
status	in	std_logic_vector(3 downto 0)
	SDRAM controller port

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