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Architecture arch of work.dualport

Defined in System09_base/sdramcntl.vhd


Libraries and global use clauses

library IEEE
use IEEE.numeric_std.all
use IEEE.std_logic_1164.all
use IEEE.std_logic_unsigned.all
library UNISIM
use WORK.common.all

Type declarations

typedoorStateis (OPENED, CLOSED)
The door signal controls whether the read/write signal from the active port is allowed through to the read/write inputs of the SDRAM controller.
typeportStateis (PORT0, PORT1)
The port signal indicates which port is connected to the SDRAM controller.

Processes

port_process (port_r, inProgress, switch, done)
Determine which port will be active on the next cycle. The active port is switched if: 1) the currently active port has finished its current R/W operation, and 2) there are no pending operations in progress, and 3) the port switch indicator is active.
door_process (door_r, inProgress, switch)
Determine if the door is open for the active port to initiate new R/W operations to the SDRAM controller. If the door is open and R/W operations are in progress but a switch to the other port is indicated, then the door is closed to prevent any further R/W operations from the active port. The door is re-opened once all in-progress operations are completed, at which time the switch to the other port is also completed so it can issue its own R/W commands.
update (rst0, rst1, clk)
update registers on the appropriate clock edge

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