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Defined in VHDL/dma6844.vhd
Author: John E. Kent
Version: 0.1 from 18th April 2010
Implements a 6844 compatible Direct Memory Access Controller. It is intended for use with 68xx compatible FPGA SoCs.
| library ieee | |
| use ieee.std_logic_1164.all | |
| use ieee.std_logic_arith.all | |
| use ieee.std_logic_unsigned.all | |
| library unisim | |
| use unisim.vcomponents.all |
| subtype | addr_subtype | is | std_logic_vector(ADDR_WIDTH-1 downto 0) |
| subtype | data_subtype | is | std_logic_vector(DATA_WIDTH-1 downto 0) |
| type | addr_type | is | array(0 to CHAN_COUNT-1) of addr_subtype |
| type | data_type | is | array(0 to CHAN_COUNT-1) of data_subtype |
| type | reg_type | is | array(0 to REG_COUNT-1) of data_subtype |
| REG_COUNT | integer = (CHAN_COUNT * 2 * ADDR_WIDTH / DATA_WIDTH) + DMA_CHAN + 3 |
| dma_reg_write ( clk, rst ) | ||||
| dma_reg_assign ( dma_in_reg ) | ||||
| Assign input register to specific register names | ||||
| dma_tx_req ( clk, rst, txreq ) | ||||
| Process Transfer Request Inputs | ||||