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Synthesizable 6844 Compatible DMA Controller
Defined in VHDL/dma6844.vhd
Author: John E. Kent
Version: 0.1 from 18th April 2010
| library ieee | |
| use ieee.std_logic_1164.all | |
| use ieee.std_logic_arith.all | |
| use ieee.std_logic_unsigned.all | |
| library unisim | |
| use unisim.vcomponents.all |
| clk | in | std_logic | |
| CPU Slave Interface | |||
| rst | in | std_logic | |
| CPU Slave Interface | |||
| rw | out | std_logic | |
| CPU Slave Interface | |||
| cs | out | std_logic | |
| CPU Slave Interface | |||
| addr | in | std_logic_vector(LOG2(CHAN_COUNT*4*ADDR_WIDTH/DATA_WIDTH)-1 downto 0) | |
| CPU Slave Interface | |||
| data_in | in | std_logic_vector(DATA_WIDTH-1 downto 0) | |
| CPU Slave Interface | |||
| data_out | out | std_logic_vector(DATA_WIDTH-1 downto 0) | |
| CPU Slave Interface | |||
| irq | out | std_logic | |
| CPU Slave Interface | |||
| breq | out | std_logic | |
| Bus Master Interface | |||
| bgnt | in | std_logic | |
| Bus Master Interface | |||
| brw | out | std_logic | |
| Bus Master Interface | |||
| bvma | out | std_logic | |
| Bus Master Interface | |||
| baddr | out | std_logic_vector(ADDR_WIDTH-1 downto 0) | |
| Bus Master Interface | |||
| txreq | in | std_logic_vector(CHAN_COUNT-1 downto 0) | |
| Device Interface | |||
| txstb | out | std_logic_vector(CHAN_COUNT-1 downto 0) | |
| Device Interface | |||
| txack | out | std_logic_vector(CHAN_COUNT-1 downto 0) | |
| Device Interface | |||
| txend | out | std_logic_vector(CHAN_COUNT-1 downto 0) | |
| Device Interface | |||