Home    --    Hierarchy    --    Packages    --    Entities    --    Instantiations    --    Sources

Architecture RTL of work.clock_dll

Defined in VHDL/clock_dll.vhd

Author: John E. Kent
Version: 1.0 from 30th May 2010


Detailed description

Implements a a system clock divider for System09.

For Xilinx Spartan 3 and 3E FPGA boards

Assumes a 12.5 MHz system clock input

Generates a x1 (12.5 MHz) CPU clock

Generates a x2 (25.0 MHz) VGA clock

Generates a x4 (50.0 MHz) MEM clock


Libraries and global use clauses

library ieee
use ieee.numeric_std.all
use ieee.std_logic_1164.all
use ieee.std_logic_arith.all
use ieee.std_logic_unsigned.all
library unisim
use unisim.vcomponents.all

Component declarations

CLKDLL
Component Declaration for CLKDLL should be placed after architecture statement but before begin keyword
IBUFG
BUFG
SRL16

Processes

clock_dll_assign ( VGA_RESET_N, VGA_LOCKED, clk_in, CPU_CLKFB, VGA_CLKFB )

Instantiations

cpu_clkin_buffer : IBUFG
cpu_clkout_buffer : BUFG
cpu_clkfb_buffer : BUFG
CLKDLL_CPU : CLKDLL
Generic map:
CLKDV_DIVIDE => 2.0
DUTY_CYCLE_CORRECTION => TRUE
STARTUP_WAIT => FALSE
vga_clkfb_buffer : BUFG
CLKDLL_VGA : CLKDLL
Generic map:
CLKDV_DIVIDE => 2.0
DUTY_CYCLE_CORRECTION => TRUE
STARTUP_WAIT => FALSE
my_srl16 : SRL16

Generated on 1 Jan 2018 19:48:42 with VHDocL V0.2.6