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Defined in VHDL/clock_dll.vhd
Author: John E. Kent
Version: 1.0 from 30th May 2010
Implements a a system clock divider for System09.
For Xilinx Spartan 3 and 3E FPGA boards
Assumes a 12.5 MHz system clock input
Generates a x1 (12.5 MHz) CPU clock
Generates a x2 (25.0 MHz) VGA clock
Generates a x4 (50.0 MHz) MEM clock
library ieee | |
use ieee.numeric_std.all | |
use ieee.std_logic_1164.all | |
use ieee.std_logic_arith.all | |
use ieee.std_logic_unsigned.all | |
library unisim | |
use unisim.vcomponents.all |
CLKDLL | ||||
Component Declaration for CLKDLL should be placed after architecture statement but before begin keyword | ||||
IBUFG | ||||
BUFG | ||||
SRL16 |
clock_dll_assign ( VGA_RESET_N, VGA_LOCKED, clk_in, CPU_CLKFB, VGA_CLKFB ) |
cpu_clkin_buffer : IBUFG | ||||||||||
cpu_clkout_buffer : BUFG | ||||||||||
cpu_clkfb_buffer : BUFG | ||||||||||
CLKDLL_CPU : CLKDLL | ||||||||||
Generic map: | ||||||||||
| ||||||||||
vga_clkfb_buffer : BUFG | ||||||||||
CLKDLL_VGA : CLKDLL | ||||||||||
Generic map: | ||||||||||
| ||||||||||
my_srl16 : SRL16 |