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Synthesible System Clock Divider for Xilinx Spartan 3
Defined in VHDL/clock_dll.vhd
Author: John E. Kent
Version: 1.0 from 30th May 2010
| library ieee | |
| use ieee.numeric_std.all | |
| use ieee.std_logic_1164.all | |
| use ieee.std_logic_arith.all | |
| use ieee.std_logic_unsigned.all | |
| library unisim | |
| use unisim.vcomponents.all |
| clk_in | in | std_Logic |
| clk_cpu | out | std_logic |
| clk_vga | out | std_logic |
| clk_mem | out | std_logic |
| locked | out | std_logic |