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Synthesizable SWTPc 6809 Dynamic Address Translation Table
Defined in VHDL/datram.vhd
Author: John E. Kent
Version: 0.4 from 2010-06-17
| library ieee | |
| use ieee.std_logic_1164.all | |
| use ieee.std_logic_unsigned.all |
| clk | in | std_logic |
| rst | in | std_logic |
| cs | in | std_logic |
| addr_hi | in | std_logic_vector(3 downto 0) |
| addr_lo | in | std_logic_vector(3 downto 0) |
| rw | in | std_logic |
| data_in | in | std_logic_vector(7 downto 0) |
| data_out | out | std_logic_vector(7 downto 0) |