Home -- Hierarchy -- Packages -- Entities -- Instantiations -- Sources |
Defined in VHDL/datram.vhd
Author: John E. Kent
Version: 0.4 from 2010-06-17
Implements a Dynamic Address Translation RAM module as found in the SWTPc MP-09 CPU card. Maps the high order 4 address bits to 8 address lines extending the memory addressing range from 64K to 1MByte. Memory segments are mapped on 4 KByte boundaries. The DAT registers are mapped at the the top of memory ($FFF0 - $FFFF) and are write only so can map behind ROM. Since the DAT is not supported by SWTBUG for the 6800, the resgisters reset state map the bottom 64K of RAM.
DAT is initialized as follows:
DAT Dat Logical Physical Reg Val Addr Addr fff0 - 0f - page 0 - $0xxx = $00xxx (RAM) fff1 - 0e - page 1 - $1xxx = $01xxx (RAM) fff2 - 0d - page 0 - $2xxx = $02xxx (RAM) fff3 - 0c - page 0 - $3xxx = $03xxx (RAM) fff4 - 0b - page 0 - $4xxx = $04xxx (RAM) fff5 - 0a - page 0 - $5xxx = $05xxx (RAM) fff6 - 09 - page 0 - $6xxx = $06xxx (RAM) fff7 - 08 - page 0 - $7xxx = $07xxx (RAM) fff8 - 07 - page 0 - $8xxx = $08xxx (RAM) fff9 - 06 - page 0 - $9xxx = $09xxx (RAM) fffa - 05 - page 0 - $axxx = $0axxx (RAM) fffb - 04 - page 0 - $bxxx = $0bxxx (RAM) fffc - 03 - page 0 - $cxxx = $0cxxx (RAM) fffd - 02 - page 0 - $dxxx = $0dxxx (RAM) fffe - f1 - page 0 - $exxx = $fexxx (I/O) ffff - f0 - page 0 - $fxxx = $ffxxx (ROM/DMFA2)
library ieee | |
use ieee.std_logic_1164.all | |
use ieee.std_logic_unsigned.all |
dat_write ( clk ) | ||||
dat_read ( addr_hi, dat_reg0, dat_reg1, dat_reg2, dat_reg3, dat_reg4, dat_reg5, dat_reg6, dat_reg7, dat_reg8, dat_reg9, dat_reg10, dat_reg11, dat_reg12, dat_reg13, dat_reg14, dat_reg15 ) |