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Synthesizable 6850 compatible ACIA
Defined in VHDL/acia6850.vhd
Author: John E. Kent
Version: 4.4 from 2010-08-27
| library ieee | |
| use ieee.numeric_std.all | |
| use ieee.std_logic_1164.all | |
| use ieee.std_logic_unsigned.all |
| clk | in | std_logic |
| rst | in | std_logic |
| cs | in | std_logic |
| addr | in | std_logic |
| rw | in | std_logic |
| data_in | in | std_logic_vector(7 downto 0) |
| data_out | out | std_logic_vector(7 downto 0) |
| irq | out | std_logic |
| RxC | in | std_logic |
| TxC | in | std_logic |
| RxD | in | std_logic |
| TxD | out | std_logic |
| DCD_n | in | std_logic |
| CTS_n | in | std_logic |
| RTS_n | out | std_logic |