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Architecture rtl of work.acia6850

Defined in VHDL/acia6850.vhd

Author: John E. Kent
Version: 4.4 from 2010-08-27

Detailed description

Implements a RS232 6850 compatible Asynchronous Communications Interface Adapter (ACIA).

Libraries and global use clauses

library ieee
use ieee.numeric_std.all
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all

Type declarations

typeDCD_State_Typeis (DCD_State_Idle, DCD_State_Int, DCD_State_Reset)
typeRxStateTypeis ( RxState_Wait, RxState_Data, RxState_Parity, RxState_Stop )
RX Signals
typeTxStateTypeis ( TxState_Idle, TxState_Start, TxState_Data, TxState_Parity, TxState_Stop )
TX Signals

Processes

acia_reset ( clk, rst, ac_rst, dcd_n )
acia_read_write (clk, ac_rst)
Generate Read / Write strobes.
acia_status ( clk )
ACIA Status Register
acia_control (CtrlReg, TxDat)
ACIA Transmit Control
acia_data_mux (Addr, RxReg, StatReg)
Set Data Output Multiplexer
acia_dcd_edge ( clk, ac_rst )
Data Carrier Detect Edge rising edge detect
acia_dcd_int ( clk, ac_rst )
Data Carrier Detect Interrupt If Data Carrier is lost, an interrupt is generated To clear the interrupt, first read the status register then read the data receive register
acia_rx_clock_edge ( clk, rx_rst )
Receiver Clock Edge Detection A rising edge will produce a one clock cycle pulse
acia_rx_data_edge ( clk, rx_rst )
Receiver Data Edge Detection A falling edge will produce a pulse on RxClk wide
acia_rx_start_stop ( clk, rx_rst )
Receiver Start / Stop Enable the receive clock on detection of a start bit Disable the receive clock after a byte is received.
acia_rx_clock_divide ( clk, rx_rst )
Receiver Clock Divider Hold the Rx Clock divider in reset when the receiver is disabled Advance the count only on a rising Rx clock edge
acia_rx_baud_clock_select ( BdFmt, RxC, RxClkCnt )
Receiver Baud Clock Selector BdFmt 0 0 - Baud Clk divide by 1 0 1 - Baud Clk divide by 16 1 0 - Baud Clk divide by 64 1 1 - Reset
acia_rx_receive ( clk, rst )
Receiver process WdFmt - Bits[4..2] 0 0 0 - 7 data, even parity, 2 stop 0 0 1 - 7 data, odd parity, 2 stop 0 1 0 - 7 data, even parity, 1 stop 0 1 1 - 7 data, odd parity, 1 stop 1 0 0 - 8 data, no parity, 2 stop 1 0 1 - 8 data, no parity, 1 stop 1 1 0 - 8 data, even parity, 1 stop 1 1 1 - 8 data, odd parity, 1 stop
acia_rx_read ( clk, rst, RxRdy )
Receiver Read process
acia_tx_clock_edge ( Clk, tx_rst )
Transmit Clock Edge Detection A falling edge will produce a one clock cycle pulse
acia_tx_clock_divide ( clk, tx_rst )
Transmit Clock Divider Advance the count only on an input clock pulse
acia_tx_baud_clock_select ( BdFmt, TxClkCnt, TxC )
Transmit Baud Clock Selector
acia_tx_transmit ( clk, tx_rst)
Implements the Tx unit WdFmt - Bits[4..2] 0 0 0 - 7 data, even parity, 2 stop 0 0 1 - 7 data, odd parity, 2 stop 0 1 0 - 7 data, even parity, 1 stop 0 1 1 - 7 data, odd parity, 1 stop 1 0 0 - 8 data, no parity, 2 stop 1 0 1 - 8 data, no parity, 1 stop 1 1 0 - 8 data, even parity, 1 stop 1 1 1 - 8 data, odd parity, 1 stop
acia_tx_write ( clk, tx_rst, TxWr, TxReq, TxAck )
Transmitter Write process
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