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Architecture trace_arch of work.trace

Implements a hardware real-time trace buffer for system09.

Defined in VHDL/trace.vhd

Author: John E. Kent
Version: 0.2 from 2010-08-09


Detailed description

Captures all the CPU bus cycles to a block RAM trace buffer. A trigger condition may be used to start or stop a trace capture. The trigger condition is determined by the address, data and control, comparator and qualifier registers. The comparator registers determine the level of the signals to trigger on. The qualifier registers determine if the comparison is to be made for that bit (qualifier bit set) or not (qualifier bit cleared). The hardware trace capture module has 9 x 8 bit registers and 5 trace buffers. Separate chip selects are provided for the register bank and trace buffer bank. The individual trace buffers are selected via the bank select register. Trace buffers may be read by the CPU but are only written to when tracing CPU bus cycles. The lowest trace buffer address always points to the start of the trace capture. This is achieved by adding an offset to the buffer address which points to the last cycle captured.


Libraries and global use clauses

library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all

Component declarations

trace_ram
Block RAM Trace buffer For Spartan 2 these will be B4 RAMs ( 512 Bytes) For Spartan 3 these will be B16 RAMs (2048 Bytes)

Processes

trace_ctrl_assign ( irq_out, qual_ctrl, rw, cpu_vma )
Assign control signal input
trace_reg_write ( clk, rst, cs_r, rw, addr, data_in )
Write Trace Registers
trace_reg_read ( addr, rw, cs_r, comp_addr_hi, comp_addr_lo, comp_data, comp_ctrl, qual_addr_hi, qual_addr_lo, qual_data, qual_ctrl, bank_reg, irq_out )
Read Trace Register (output mux)
trace_buf_read ( bank_reg, buf_data_out_0, buf_data_out_1, buf_data_out_2, buf_data_out_3, buf_data_out_4 )
Read Trace Buffers
trace_read ( cs_r, reg_data_out, buf_data_out )
Read Registers or Buffers
trace_buf_mux ( cs_b, trace_count, trace_en, buf_addr )
Multiplex the trace buffer between the trace capture and the CPU read
trace_trigger ( clk, rst, cs_r, addr, rw, cpu_vma, data_in, cpu_data_in, comp_addr_hi, comp_addr_lo, comp_data, comp_ctrl, qual_addr_hi, qual_addr_lo, qual_data, qual_ctrl)
Trigger comparator process
trace_capture ( clk, rst, addr, qual_write, trigger, trace_en, qual_ctrl, irq_out, trace_count, trace_offset )
Trace buffer capture on event trigger

Instantiations

trace_buffer_0 : trace_ram
trace_buffer_1 : trace_ram
Bank 1 - Trace buffer for CPU address low bits
trace_buffer_2 : trace_ram
Bank 2 - Trace buffer for CPU data out (write)
trace_buffer_3 : trace_ram
Bank 3 - Trace buffer for CPU data in (read)
trace_buffer_4 : trace_ram
Bank 4 - Trace buffer for CPU control bits

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