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Architecture RTL of work.clock_div

Defined in VHDL/clock_div.vhd

Author: John E. Kent
Version: 0.2 from 2010-09-14


Detailed description

Generates Clocks for System09

For BurchED B3-Spartan2+ and B5-X300

Divides the input clock which is normally 50MHz

Generates a 1/1 (50.0 MHz) SYS clock

Generates a 1/2 (25.0 MHz) VGA clock

Generates a 1/4 (12.5 MHz) CPU clock


Libraries and global use clauses

library ieee
use ieee.numeric_std.all
use ieee.std_logic_1164.all
use IEEE.STD_LOGIC_ARITH.ALL
use IEEE.STD_LOGIC_UNSIGNED.ALL

Component declarations

BUFG

Processes

clock_div ( clk_in )
Clock divider

Instantiations

sys_clk_buffer : BUFG
vga_clk_buffer : BUFG
cpu_clk_buffer : BUFG

Generated on 1 Jan 2018 19:48:42 with VHDocL V0.2.6