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Synthesizable Simple Parallel Port
Defined in VHDL/spp.vhd
Author: John E. Kent
Version: 0.2 from 2010-08-09
library ieee | |
use ieee.std_logic_1164.all | |
use ieee.std_logic_unsigned.all |
clk | in | std_logic |
rst | in | std_logic |
cs | in | std_logic |
rw | in | std_logic |
addr | in | std_logic_vector(2 downto 0) |
data_in | in | std_logic_vector(7 downto 0) |
data_out | out | std_logic_vector(7 downto 0) |
spp_data | out | std_logic_vector(7 downto 0) |
spp_stat | in | std_logic_vector(7 downto 3) |
spp_ctrl | out | std_logic_vector(3 downto 0) |
hold | out | std_logic |
irq | out | std_logic |