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Synthesizable Serial Peripheral Interface Master
Defined in VHDL/spi-master.vhd
Authors: Hans Huebner and John E. Kent
Version: 0.2 from 16 June 2010
| library ieee | |
| use ieee.std_logic_1164.all | |
| use ieee.std_logic_unsigned.all |
| clk | in | std_logic | |
| CPU Interface Signals | |||
| reset | in | std_logic | |
| CPU Interface Signals | |||
| cs | in | std_logic | |
| CPU Interface Signals | |||
| rw | in | std_logic | |
| CPU Interface Signals | |||
| addr | in | std_logic_vector(1 downto 0) | |
| CPU Interface Signals | |||
| data_in | in | std_logic_vector(7 downto 0) | |
| CPU Interface Signals | |||
| data_out | out | std_logic_vector(7 downto 0) | |
| CPU Interface Signals | |||
| irq | out | std_logic | |
| CPU Interface Signals | |||
| spi_miso | in | std_logic | |
| SPI Interface Signals | |||
| spi_mosi | out | std_logic | |
| SPI Interface Signals | |||
| spi_clk | out | std_logic | |
| SPI Interface Signals | |||
| spi_cs_n | out | std_logic_vector(7 downto 0) | |
| SPI Interface Signals | |||