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Entity work.pia_timer

Synthesizable Parallel Interface Adapter with Timer

Defined in VHDL/pia_timer.vhd

Author: John E. Kent
Version: 1.2 from 30th May 2010

Architectures

pia_arch


Libraries and global use clauses

library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all
library unisim
use unisim.vcomponents.all

Ports

clk instd_logic
rst instd_logic
cs instd_logic
rw instd_logic
addr instd_logic_vector(1 downto 0)
data_in instd_logic_vector(7 downto 0)
data_out outstd_logic_vector(7 downto 0)
irqa outstd_logic
irqb outstd_logic

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