Home -- Hierarchy -- Packages -- Entities -- Instantiations -- Sources |
Synthesizable 6821 Compatible Parallel Interface Adapter
Defined in VHDL/pia6821.vhd
Author: John E. Kent
Version: 0.2 from 2010-08-09
library ieee | |
use ieee.std_logic_1164.all | |
use ieee.std_logic_unsigned.all |
clk | in | std_logic |
rst | in | std_logic |
cs | in | std_logic |
rw | in | std_logic |
addr | in | std_logic_vector(1 downto 0) |
data_in | in | std_logic_vector(7 downto 0) |
data_out | out | std_logic_vector(7 downto 0) |
irqa | out | std_logic |
irqb | out | std_logic |
pa | inout | std_logic_vector(7 downto 0) |
ca1 | in | std_logic |
ca2 | inout | std_logic |
pb | inout | std_logic_vector(7 downto 0) |
cb1 | in | std_logic |
cb2 | inout | std_logic |