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Defined in VHDL/SevenSegmentDisplay.vhd
| library IEEE | |
| use IEEE.STD_LOGIC_1164.ALL | |
| use IEEE.STD_LOGIC_ARITH.ALL | |
| use IEEE.STD_LOGIC_UNSIGNED.ALL |
| Clk | in | std_logic |
| Reset | in | std_logic |
| Value0 | in | std_logic_vector(3 downto 0) |
| Value1 | in | std_logic_vector(3 downto 0) |
| Value2 | in | std_logic_vector(3 downto 0) |
| Value3 | in | std_logic_vector(3 downto 0) |
| DPs | in | std_logic_vector(3 downto 0) |
| Blanks | in | std_logic_vector(3 downto 0) |
| DigitSelect | out | std_logic_vector(3 downto 0) |
| Segments | out | std_logic_vector(7 downto 0) |