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Defined in VHDL/epp.vhd
Author: John E. Kent
Version: 0.2 from 2010-08-09
Implements an Enhanced Parallel Port Interface
| library ieee | |
| use ieee.std_logic_1164.all | |
| use ieee.std_logic_unsigned.all | |
| library unisim | |
| use unisim.vcomponents.all |
| CTRL_RW_BIT | integer | |
| CTRL_DS_BIT | integer | := 1 |
| CTRL_RS_BIT | integer | := 2 |
| CTRL_AS_BIT | integer | := 3 |
| STAT_IR_BIT | integer | := 6 |
| STAT_WT_BIT | integer | := 7 |
| epp_control ( rst, clk, cs, rw, addr, epp_stat, epp_crl_reg, data_in ) |