| Home -- Hierarchy -- Packages -- Entities -- Instantiations -- Sources |
Synthesizable 6809 instruction compatible VHDL CPU core
Defined in VHDL/cpu09.vhd
Author: John E. Kent
Version: 1.19 from 25th February 2008
6809 instruction compatible CPU core written in VHDL. Not cycle compatible with the original 6809 CPU.
| library ieee | |
| use ieee.std_logic_1164.all | |
| use ieee.std_logic_unsigned.all |
| clk | in | std_logic |
| rst | in | std_logic |
| vma | out | std_logic |
| addr | out | std_logic_vector(15 downto 0) |
| rw | out | std_logic |
| data_out | out | std_logic_vector(7 downto 0) |
| data_in | in | std_logic_vector(7 downto 0) |
| irq | in | std_logic |
| firq | in | std_logic |
| nmi | in | std_logic |
| halt | in | std_logic |
| hold | in | std_logic |