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Defined in VHDL/peripheral_bus.vhd
Author: John E. Kent
Version: 0.1 from 2010-08-28
Implements a 16 bit peripheral bus interface On the XESS XST-3.0 carrier board it is shared by an IDE interface, and Ethernet MAC and two 16 bit expansion slots. The same bus structure is used on the BurchED B3 and B5-X300 Spartan 2 boards to implement an IDE Compact Flash interface.
The 16 bit data bus is accessed by two consecutive byte wide read or write cycles.
On an even byte read a read strobe is generated on the peripheral bus and the high bits of the peripheral data bus are output to the CPU data bus and the lower 8 bits latched. A bus hold cycle is generated to allow time for the peripheral data bus to settle. On the odd byte read, the latched lower data bits of the peripheral bus are output on the CPU data bus.
Conversely, on an even byte write the CPU data bus value is latched. On the odd byte write, the latched value is output to the high 8 bits of the peripheral bus, and the CPU data is output to the lower 8 bits of the peripheral bus and a peripheral write strobe is generated. A hold signal is geneated back to the CPU to allow the peripheral bus to settle.
| library ieee | |
| use ieee.numeric_std.all | |
| use ieee.std_logic_1164.all | |
| use ieee.std_logic_unsigned.all |
| type | hold_state_type | is | ( hold_release_state, hold_request_state ) |
| peripheral_bus_decode ( addr, cs ) | ||||
| peripheral_bus_control ( clk, rst, cs, addr, rw, data_in, pb_hold, pb_wreg, pb_rreg, pb_wru, pb_wrl, pb_rdu, pb_rdl, pb_data ) | ||||
| 16-bit Peripheral Bus 6809 Big endian ISA bus little endian Not sure about IDE interface | ||||
| peripheral_bus_hold ( clk, rst, cs, pb_hold_state, pb_hold, pb_rdu, pb_wrl ) | ||||
| Hold Peripheral bus accesses for a few cycles | ||||